Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758190AbYFCSzy (ORCPT ); Tue, 3 Jun 2008 14:55:54 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1753176AbYFCSzo (ORCPT ); Tue, 3 Jun 2008 14:55:44 -0400 Received: from palinux.external.hp.com ([192.25.206.14]:36269 "EHLO mail.parisc-linux.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751624AbYFCSzn (ORCPT ); Tue, 3 Jun 2008 14:55:43 -0400 Date: Tue, 3 Jun 2008 12:55:41 -0600 From: Matthew Wilcox To: Trent Piepho Cc: Linus Torvalds , Nick Piggin , Russell King , Benjamin Herrenschmidt , David Miller , linux-arch@vger.kernel.org, scottwood@freescale.com, linuxppc-dev@ozlabs.org, alan@lxorguk.ukuu.org.uk, linux-kernel@vger.kernel.org Subject: Re: MMIO and gcc re-ordering issue Message-ID: <20080603185541.GB3549@parisc-linux.org> References: <1211852026.3286.36.camel@pasglop> <20080602072403.GA20222@flint.arm.linux.org.uk> <200806031416.18195.nickpiggin@yahoo.com.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.13 (2006-08-11) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1663 Lines: 38 On Tue, Jun 03, 2008 at 11:47:00AM -0700, Trent Piepho wrote: > On Tue, 3 Jun 2008, Linus Torvalds wrote: > >On Tue, 3 Jun 2008, Nick Piggin wrote: > >> > >>Linus: on x86, memory operations to wc and wc+ memory are not ordered > >>with one another, or operations to other memory types (ie. load/load > >>and store/store reordering is allowed). Also, as you know, store/load > >>reordering is explicitly allowed as well, which covers all memory > >>types. So perhaps it is not quite true to say readl/writel is strongly > >>ordered by default even on x86. You would have to put in some > >>mfence instructions in them to make it so. > > So on x86, these could be re-ordered? > > writel(START_OPERATION, CONTROL_REGISTER); > status = readl(STATUS_REGISTER); You wouldn't ask for write-combining memory mapping for control or status registers. > >Well, you have to ask for WC/WC+ anyway, so it's immaterial. A driver that > >does that needs to be aware of it. IOW, it's a non-issue, imnsho. > > You need to ask for coherent DMA memory too. Different case. Coherent DMA memory is *host* memory that the *device* accesses. We're talking about *device* memory that the *cpu* accesses. -- Intel are signing my paycheques ... these opinions are still mine "Bill, look, we understand that you're interested in selling us this operating system, but compare it to ours. We can't possibly take such a retrograde step." -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/