Date: Thu, 12 Jun 2008 22:04:05 +0300
From: Heikki Orsila <shdl@zakalwe.fi>
To: David Altobelli <david.altobelli@hp.com>
Cc: linux-kernel@vger.kernel.org
Subject: Re: [PATCH] HP iLO driver
Message-ID: <20080612190405.GR31039@zakalwe.fi>
References: <20080612182308.GA1091@ldl.fc.hp.com>
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On Thu, Jun 12, 2008 at 12:23:08PM -0600, David Altobelli wrote:
> +struct fifo {
> +    u64 nrents;	/* user requested number of fifo entries */
> +    u64 imask;  /* mask to extract valid fifo index */
> +    u64 merge;	/*  O/C bits to merge in during enqueue operation */
> +    u64 reset;	/* set to non-zero when the target device resets */
> +    u8  pad_0[ILO_CACHE_SZ - (sizeof(u64) * 4)];
> +
> +    u64 head;
> +    u8  pad_1[ILO_CACHE_SZ - (sizeof(u64))];
> +
> +    u64 tail;
> +    u8  pad_2[ILO_CACHE_SZ - (sizeof(u64))];
> +
> +    volatile u64 fifobar[1];
> +};

Why do you need a volatile? What you probably want is atomic ops. 
Spinlocks will create memory barriers implicitly.

> +static int fifo_enqueue(struct ilo_hwinfo *hw, char *fifobar, int entry)
> +{
> +	struct fifo *Q = FIFOBARTOHANDLE(fifobar);
> +	int ret = 0;
> +
> +	spin_lock(&hw->fifo_lock);
> +	if (!(Q->fifobar[(Q->tail + 1) & Q->imask] & ENTRY_MASK_O)) {
> +		Q->fifobar[Q->tail & Q->imask] |=
> +			((entry & ENTRY_MASK_NOSTATE) | Q->merge);
> +		Q->tail += 1;
> +		ret = 1;
> +	}
> +	spin_unlock(&hw->fifo_lock);
> +
> +	return ret;
> +}

Is writing to Q->fifobar (u64 *) endian-safe?

-- 
Heikki Orsila
heikki.orsila@iki.fi
http://www.iki.fi/shd
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