Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758985AbYFMMi7 (ORCPT ); Fri, 13 Jun 2008 08:38:59 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1755529AbYFMMit (ORCPT ); Fri, 13 Jun 2008 08:38:49 -0400 Received: from www.tglx.de ([62.245.132.106]:39537 "EHLO www.tglx.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755460AbYFMMit (ORCPT ); Fri, 13 Jun 2008 08:38:49 -0400 Date: Fri, 13 Jun 2008 14:38:30 +0200 (CEST) From: Thomas Gleixner To: Andreas Herrmann cc: LKML , Ingo Molnar , Arjan van de Veen Subject: Re: [patch 3/6] x86: use cpuinfo to check for interrupt pending message msr In-Reply-To: <20080613065524.GE7763@alberich.amd.com> Message-ID: References: <20080610171639.551369443@linutronix.de> <20080610171712.304283554@linutronix.de> <20080613065524.GE7763@alberich.amd.com> User-Agent: Alpine 1.10 (LFD 962 2008-03-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 708 Lines: 21 On Fri, 13 Jun 2008, Andreas Herrmann wrote: > > + /* Family 0x0f models < rev F do not have this MSR */ > > + if (c->x86 == 0x0f && c->x86_model < 0x40) > > + return 0; > > Just some minor nitpicking. > Older AMD family 0xf CPUs have this Interrupt Pending Message > Register. But they do not support C1E and thus bits 27 and 28 of this > MSR are reserved. So the check can be simplified to always check the MSR for all family >= 0x0f CPUs ? Thanks, tglx -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/