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Subject: Re: [PATCH] IBM Lanstreamer bugfixes
To: yoder1@us.ibm.com (Kent E Yoder)
Date: Fri, 18 Jan 2002 23:19:08 +0000 (GMT)
Cc: alan@lxorguk.ukuu.org.uk (Alan Cox),
        jgarzik@mandrakesoft.com (Jeff Garzik), linux-kernel@vger.kernel.org
In-Reply-To: <OF0DC8C676.D07D3CD8-ON85256B45.007E1B7C@raleigh.ibm.com> from "Kent E Yoder" at Jan 18, 2002 05:02:57 PM
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From: Alan Cox <alan@lxorguk.ukuu.org.uk>
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>   BTW, I don't know what PCI posting effects are...

Ok given

	writel(foo, dev->reg);
	udelay(5);
	writel(bar, dev->reg);

The pci bridge is at liberty to delay the first write until the second or a
read from that device comes along (and wants to do so to merge bursts). It
tends to bite people

	-	When they do a write to clear the IRQ status and don't do
		a read so they keep handling lots of phantom level triggered
		interrupts.

	-	When there is a delay (reset is common) that has to be observed

	-	At the end of a DMA transfer when people unmap stuff early
		and the "stop the DMA" command got delayed

Alan
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