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Date: Tue, 22 Jan 2002 01:37:43 +0100
From: Andrea Arcangeli <andrea@suse.de>
To: "David S. Miller" <davem@redhat.com>
Cc: reid.hekman@ndsu.nodak.edu, linux-kernel@vger.kernel.org, akpm@zip.com.au,
        alan@lxorg.ukuu.org
Subject: Re: Athlon PSE/AGP Bug
Message-ID: <20020122013743.M8292@athlon.random>
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In-Reply-To: <20020121.141931.105134927.davem@redhat.com>; from davem@redhat.com on Mon, Jan 21, 2002 at 02:19:31PM -0800
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On Mon, Jan 21, 2002 at 02:19:31PM -0800, David S. Miller wrote:
>    From: Andrea Arcangeli <andrea@suse.de>
>    Date: Mon, 21 Jan 2002 17:54:10 +0100
>    
>    correct, furthmore it cannot even trigger if you invlpg with an address
>    page aligned (4mbyte aligned in this case) like we would always do in
>    linux anyways, we never use invlpg on misaligned addresses, no matter if
>    the page is a 4M or a 4k page.
> 
> That's not true, see the ptrace() helper code.  Russell King pointed
> this out to me last week and it's on my TODO list to fix it up.

Where? :) ptrace doesn't change pagetables, no need to flush any tlb in
ptrace.

Anyways if the problem is in the nvidia driver they may be really doing
an invlpg on a misaligned 4M page address for no good reason, this
sounds unlikely though.  What's certain is that the stuff into the
mainline kernel shouldn't really be affected for the reason you also
said previously (we never invalidate 4M pages with invlpg). In the very
worst case nvidia guys just need to mask the lower (not significant)
bits before passing the address to invlpg, which is going to be a one
liner.

Andrea
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