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From: 520047054719-0001@t-online.de (Oliver Neukum)
Reply-To: Oliver.Neukum@lrz.uni-muenchen.de
To: "David S. Miller" <davem@redhat.com>, drobbins@gentoo.org
Subject: Re: Athlon/AGP issue update
Date: Wed, 23 Jan 2002 20:20:44 +0100
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On Wednesday 23 January 2002 11:18, David S. Miller wrote:
> This means that the fix belongs in the DRM drivers, specifically
> DRM(mmap_dma) should clear the cacheability bits in the
> vma->vm_page_prot at mmap time.

Is that sufficient ? Must the cache be flushed explicitely ?

[..]
> Disabling 4MB translations has zero effect on the problem they say is
> the root all of this.  The mappings given to the OpenGL driver to the
> GART memory is still going to be cacheable, thus the problem ought to
> still exist.
>
> As usual, AMD's commentary brings more questions than it answers.

Perhaps speculative writes require an entry in the TLB making it less likely 
that they'll happen to 4KB pages.

	Regards
		Oliver
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