Message-ID: <4889948D.7020408@jp.fujitsu.com>
Date: Fri, 25 Jul 2008 17:53:33 +0900
From: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
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To: Matthew Wilcox <matthew@wil.cx>
CC: Pierre Ossman <drzeus-list@drzeus.cx>, Alex Chiang <achiang@hp.com>,
       Jesse Barnes <jbarnes@virtuousgeek.org>,
       LKML <linux-kernel@vger.kernel.org>, linux-pci@vger.kernel.org
Subject: Re: post 2.6.26 requires pciehp_slot_with_bus
References: <20080724134737.4b91f30d@mjolnir.drzeus.cx> <200807241407.18543.jbarnes@virtuousgeek.org> <20080724235127.40bd0ac9@mjolnir.drzeus.cx> <200807241506.58973.jbarnes@virtuousgeek.org> <20080724222914.GG5307@ldl.fc.hp.com> <20080725004926.5f201c70@mjolnir.drzeus.cx> <20080724230827.GA30302@ldl.fc.hp.com> <20080725012916.06679a6d@mjolnir.drzeus.cx> <20080725032909.GA6701@parisc-linux.org>
In-Reply-To: <20080725032909.GA6701@parisc-linux.org>
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Matthew Wilcox wrote:
> On Fri, Jul 25, 2008 at 01:29:16AM +0200, Pierre Ossman wrote:
>> On Thu, 24 Jul 2008 17:08:27 -0600
>> Alex Chiang <achiang@hp.com> wrote:
>>
>>> Sorry for one more round-trip, but could you turn on debugging
>>> for pciehp as well?
>>>
>> Same thing, with debugging:
> 
> I have a laptop with a similar problem (though I don't have pciehp
> enabled, so I didn't notice it).  Obviously, we need to fix this.
> 
> There is no question in my mind that firmware has programmed the slot
> numbers incorrectly.  Here's the evidence from lspci -vvv:
> 
> 00:1c.0 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 1 (rev 03)
>         Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00
>                 SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surpise+
>                         Slot #  2, PowerLimit 6.500000; Interlock- NoCompl-
> 00:1c.4 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 5 (rev 03)
>         Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00
>                 SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surpise+
>                         Slot #  2, PowerLimit 6.500000; Interlock- NoCompl-
> 
> I don't think anyone can credibly argue that this is correct.  They're
> both PCIe devices, they're both both indicating that they have a slot
> (maybe if I get my screwdriver out, I can see if there's really a slot
> ...), they're on the same bus (so I don't know how the with_bus
> parameter makes any difference).
> 

FYI:

IIRC, pciehp uses bridge's secondary bus number for slot name, and
PCI express downstream port can have only one hotplug slot. I think
this is why with_bus prameter makes difference. But it doesn't work
on the system that has multiple pci segments. In addition, shpchp
also has with_bus option, but it doesn't work because shpc controller
can have multiple slots on the bridge's secondary bus. Anyway, as
you mentioned, using bus number for slot name is obviously not good
idea, and your idea (e.g. "2-1", "2-2") looks much better.

Thanks,
Kenji Kaneshige


> I've always hated that with_bus parameter.  I don't like it being a
> parameter and I don't like the names it produces.
> 
> Part of the problem is the kobject API.  It really hates you trying to
> register a duplicate name and won't just return -EEXIST and let you try
> a new name.  Instead it prints an ugly warning and dumps stack.  See
> kobject_add_internal() in lib/kobject.c.
> 
> So we need a way to find if there's already a slot of this name.  I
> don't see a kobject routine to do that.  Maybe we can do it internally
> to the pci slot code.
> 
> Then we need to pick a new name for the kobject if it does collide.
> My suggestion is that the second time we find an object named "2", we
> call it "2dup1" (the third time "2dup2", etc.)  Other opinions I've
> seen include "2a", "2b", ... or "2-1", "2-2", ... or "2-brokenfw1",
> "2-brokenfw2".
> 
> I'm at OLS this week, so no patch from me.
> 


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