Date: Wed, 6 Aug 2008 08:38:45 -0600
From: Matthew Wilcox <matthew@wil.cx>
To: Grant Grundler <grundler@parisc-linux.org>
Cc: jbarnes@virtuousgeek.org, linux-kernel@vger.kernel.org, eric@anholt.net,
       Matthew Wilcox <willy@linux.intel.com>
Subject: Re: [PATCH 3/3] PCI: Add pci_read_base() API
Message-ID: <20080806143844.GL2055@parisc-linux.org>
References: <1217266741-26519-1-git-send-email-matthew@wil.cx> <1217266741-26519-4-git-send-email-matthew@wil.cx> <20080804063833.GA21354@colo.lackof.org>
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On Mon, Aug 04, 2008 at 12:38:33AM -0600, Grant Grundler wrote:
> On Mon, Jul 28, 2008 at 01:39:01PM -0400, Matthew Wilcox wrote:
> > Some devices have a BAR at a non-standard address.  The pci_read_base()
> > API allows us to probe these BARs and fill in a resource for it as if
> > they were standard BARs.
> 
> Willy,
> Can you add a comment to the code listing the offending device?
> That way we know how to test next time this code changes.

It's not an offending device -- devices are allowed to put whatever they
want anywhere outside the first 0x40 bytes of config space.

Eric Anholt's patches add a user for this interface.  If you want to see an
example, download the Intel 3 Series Express Chipset Family Datashee
(the filename is 316966.pdf) and see section 5.1.13 about the MCHBAR.

-- 
Intel are signing my paycheques ... these opinions are still mine
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours.  We can't possibly take such
a retrograde step."
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