Date: Thu, 14 Aug 2008 10:10:42 -0700
From: Greg KH <greg@kroah.com>
To: Mark Langsdorf <mark.langsdorf@amd.com>
Cc: Pavel Machek <pavel@suse.cz>, joachim.deguara@amd.com, gregkh@ucw.cz,
       tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
       linux-kernel@vger.kernel.org
Subject: Re: [PATCH 01/01][retry 5] x86: L3 cache index disable for 2.6.26
Message-ID: <20080814171042.GA26985@kroah.com>
References: <200807181603.52332.mark.langsdorf@amd.com> <200808131502.42611.mark.langsdorf@amd.com> <200808140923.50783.mark.langsdorf@amd.com> <200808141148.38108.mark.langsdorf@amd.com>
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On Thu, Aug 14, 2008 at 11:48:37AM -0500, Mark Langsdorf wrote:
> New versions of AMD processors have support to disable parts
> of their L3 caches if too many MCEs are generated by the
> L3 cache. ?
>   
> This patch provides a /sysfs interface under the cache
> hierarchy to display which caches indices are disabled
> (if any) and to monitoring applications to disable a
> cache index.
>   
> This patch does not set an automatic policy to disable
> the L3 cache. ?Policy decisions would need to be made
> by a RAS handler. ?This patch merely makes it easier to
> see what indices are currently disabled.
>   
> Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
>  
> diff -r e683983d4dd0 Documentation/ABI/testing/sysfs-devices-cache_disable
> --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
> +++ b/Documentation/ABI/testing/sysfs-devices-cache_disable	Thu Aug 14 03:49:19 2008 -0500
> @@ -0,0 +1,18 @@
> +What:           /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X
> +Date:           August 2008
> +KernelVersion:  2.6.27
> +Contact:        mark.langsdorf@amd.com
> +Description:    These files exist in every cpu's cache index directories.
> +		There are currently 2 cache_disable_# files in each 
> +		directory.  Reading from these files on a supported
> +		processor will return that cache disable index value
> +		for that processor and node.  Writing to one of these
> +		files will cause the specificed cache index to be disabled.
> +
> +		Currently, only AMD Family 10h Processors support cache index 
> +		disable, and only for their L3 caches.  See the BIOS and
> +		Kernel Developer's Guide at
> +		http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF
> +		for formatting information and other details on the
> +		cache index disable.
> +Users:          joachim.deguara@amd.com
> diff -r e683983d4dd0 arch/x86/kernel/cpu/intel_cacheinfo.c
> --- a/arch/x86/kernel/cpu/intel_cacheinfo.c	Tue Aug 12 08:46:38 2008 -0500
> +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c	Thu Aug 14 06:23:13 2008 -0500
> @@ -16,6 +16,9 @@
>  
>  #include <asm/processor.h>
>  #include <asm/smp.h>
> +
> +#include <linux/pci.h>
> +#include <asm/k8.h>
>  
>  #define LVL_1_INST	1
>  #define LVL_1_DATA	2
> @@ -130,6 +133,7 @@ struct _cpuid4_info {
>  	union _cpuid4_leaf_ebx ebx;
>  	union _cpuid4_leaf_ecx ecx;
>  	unsigned long size;
> +	unsigned long can_disable;

Why use an unsigned long for a single bit value?  bool perhaps?

thanks,

greg k-h
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