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Date: Tue, 29 Jan 2002 09:07:51 +0100 (CET)
From: Daniel Nofftz <nofftz@castor.uni-trier.de>
X-X-Sender: nofftz@infcip10.uni-trier.de
To: "Calin A. Culianu" <calin@ajvar.org>
cc: Alan Cox <alan@lxorguk.ukuu.org.uk>,
        Steven Hassani <hassani@its.caltech.edu>,
        <linux-kernel@vger.kernel.org>
Subject: Re: Athlon Optimization Problem
In-Reply-To: <Pine.LNX.4.30.0201281551250.2376-100000@rtlab.med.cornell.edu>
Message-ID: <Pine.LNX.4.40.0201290900490.7168-100000@infcip10.uni-trier.de>
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On Mon, 28 Jan 2002, Calin A. Culianu wrote:

> Hmm.  What do you recommend?  I remember seeing a spec sheet and register
> 0x95 was the memory write queue timer.. but I could have dreamed it..
>
> Anyone know what register 0x95 does?

hmmm ... when i was working on the athlon disconnect patch i found that
the pcr files (resorce files) for the wpcredit programm (windows tool for
changing the configuration of chipset) are a good source of information.
but this register isn't discribed in this file ... sorry

daniel
(i placed the pcr file on the web, if you are interested, have a look at:
http://cip.uni-trier.de/nofftz/linux/kt266_pcr.txt ... the webserver is
down at the moment, but should be up again in 1-2 hours)


# Daniel Nofftz
# Sysadmin CIP-Pool Informatik
# University of Trier(Germany), Room V 103
# Mail: daniel@nofftz.de

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