Date: Thu, 21 Aug 2008 13:01:10 +0100 (BST)
From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: Vegard Nossum <vegard.nossum@gmail.com>
cc: "Rafael J. Wysocki" <rjw@sisk.pl>, Frans Pop <elendil@planet.nl>,
       linux-kernel@vger.kernel.org, Andi Kleen <andi@firstfloor.org>,
       Ingo Molnar <mingo@elte.hu>
Subject: Re: 2.6.27-rc3: 'APIC error on CPU1: 00(40)', but only on resume!
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On Thu, 21 Aug 2008, Maciej W. Rozycki wrote:

>  Otherwise there is no correlation between the sequence of APIC writes and
> an error triggering -- a bad vector in a LVT or interrupt redirection
> entry will be reported whenever its associated interrupt line gets active
> even though the entry might have been initialised long ago.  Depending on
> the device signalling hardware interrupts may quite often be ignored for a
> long time without affecting the stability of the rest of the system.

 The same applies to a broken MSI or HT setup too; I am not sure what 
other sources of APIC interrupts may have been imaginatively added to 
maintain the proper complexity of x86 systems as well.

  Maciej
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