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Message-ID: <21d7e9970808260005g14ec71e9xfa584780498a86e7@mail.gmail.com>
Date: Tue, 26 Aug 2008 17:05:48 +1000
From: "Dave Airlie" <airlied@gmail.com>
To: venkatesh.pallipadi@intel.com
Subject: Re: [patch 3/4] x86: PAT Update validate_pat_support for intel CPUs
Cc: mingo@elte.hu, tglx@linutronix.de, hpa@zytor.com,
       linux-kernel@vger.kernel.org, suresh.b.siddha@intel.com
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On Thu, Aug 21, 2008 at 9:45 AM,  <venkatesh.pallipadi@intel.com> wrote:
> Pentium III and Core Solo/Duo CPUs have an erratum
> " Page with PAT set to WC while associated MTRR is UC may consolidate to UC "
> which can result in WC setting in PAT to be ineffective. We will disable
> PAT on such CPUs, so that we can continue to use MTRR WC setting.
>

IMHO this seems like a bit hammer with which to squash this nut.

I really need PAT support for upcoming GPU stuff, esp where I have
pages of RAM allocated into a
GART and I want write-combined access to them. These pages will
physically me under a write-back MTRR, with a WC PAT entry
on the PTE mappings.

Can we not just be smarter and fix this when we know we have a UC MTRR
and a WC PAT mapping inside it?

Dave.

> Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
>
> ---
>  arch/x86/kernel/cpu/addon_cpuid_features.c |   17 +++++++++++++++--
>  1 file changed, 15 insertions(+), 2 deletions(-)
>
> Index: tip/arch/x86/kernel/cpu/addon_cpuid_features.c
> ===================================================================
> --- tip.orig/arch/x86/kernel/cpu/addon_cpuid_features.c 2008-08-20 14:25:18.000000000 -0700
> +++ tip/arch/x86/kernel/cpu/addon_cpuid_features.c      2008-08-20 14:26:39.000000000 -0700
> @@ -56,9 +56,22 @@ void __cpuinit validate_pat_support(stru
>
>        switch (c->x86_vendor) {
>        case X86_VENDOR_INTEL:
> -               if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
> +               /*
> +                * There is a known erratum on Pentium III and Core Solo
> +                * and Core Duo CPUs.
> +                * " Page with PAT set to WC while associated MTRR is UC
> +                *   may consolidate to UC "
> +                * Because of this erratum, it is better to stick with
> +                * setting WC in MTRR rather than using PAT on these CPUs.
> +                *
> +                * Enable PAT WC only on P4, Core 2 or later CPUs.
> +                */
> +               if (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 15))
>                        return;
> -               break;
> +
> +               pat_disable("PAT WC disabled due to known CPU erratum.");
> +               return;
> +
>        case X86_VENDOR_AMD:
>        case X86_VENDOR_CENTAUR:
>        case X86_VENDOR_TRANSMETA:
>
> --
>
> --
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