Message-ID: <48EF2CE0.3080109@firstfloor.org>
Date: Fri, 10 Oct 2008 12:22:24 +0200
From: Andi Kleen <andi@firstfloor.org>
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To: Nick Piggin <nickpiggin@yahoo.com.au>
CC: Dave Jones <davej@redhat.com>, x86@kernel.org,
       Linux Kernel <linux-kernel@vger.kernel.org>
Subject: Re: Update cacheline size on X86_GENERIC
References: <20081009171453.GA15321@redhat.com> <200810101428.23662.nickpiggin@yahoo.com.au> <87tzbksxja.fsf@basil.nowhere.org> <200810101945.32111.nickpiggin@yahoo.com.au>
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Nick Piggin wrote:

> 
>>> Anyway, GENERIC kernel should run well on all architectures, and while
>>> going too big causes slightly increased structures sometimes, going too
>>> small could result in horrible bouncing.
>> Exactly.
>>
>> That is it costs one percent or so on TPC, but I think the fix
>> for that is just to analyze where the problem is and size those
>> data structures based on the runtime cache size. Some subsystems
>> like slab do this already.
> 
> Costs 1% on TPC? Is that 128 byte aligning data structures on
> Core2, or 64 byte aligning them on P4 that costs the performance?

The first. BTW it was a rough number from memory, in that ballpark.
Also the experiment was on older kernels, might be different now.

The second would undoubtedly be much worse.

-Andi
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