Message-ID: <48EF9E6F.5050006@kernel.org>
Date: Fri, 10 Oct 2008 11:26:55 -0700
From: "H. Peter Anvin" <hpa@kernel.org>
Organization: Linux Kernel Organization, Inc.
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To: Nick Piggin <nickpiggin@yahoo.com.au>
CC: Dave Jones <davej@redhat.com>, x86@kernel.org,
       Linux Kernel <linux-kernel@vger.kernel.org>
Subject: Re: Update cacheline size on X86_GENERIC
References: <20081009171453.GA15321@redhat.com> <200810101428.23662.nickpiggin@yahoo.com.au>
In-Reply-To: <200810101428.23662.nickpiggin@yahoo.com.au>
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Nick Piggin wrote:
> I think P4 technically did have 64 byte cachelines, but had some adjacent
> line prefetching. And AFAIK core2 CPUs can do similar prefetching (but
> maybe it's smarter and doesn't cause so much bouncing?).
> 
> Anyway, GENERIC kernel should run well on all architectures, and while
> going too big causes slightly increased structures sometimes, going too
> small could result in horrible bouncing.

Well, GENERIC really is targetted toward the commercial mainstream at 
the time, with the additional caveat that it shouldn't totally suck on 
anything that isn't so obscure it's irrelevant.  It is thus a moving 
target.  1% on TPC doesn't count as "totally suck", especially since by 
now anyone who is running workloads like TPC either will have phased out 
their P4s or they don't care about performance at all.

> Lastly, I think x86 will go to 128 byte lines in the next year or two, so
> maybe at this point we can just keep 128 byte alignment?

"x86" doesn't have a cache line size; a specific implementation will. 
Which particular implementation do you believe is going to 128-byte L1 
cachelines?

	-hpa
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