Subject: Re: [PATCH 0/3] Improve TSC as a clocksource under VMware
From: Alok Kataria <akataria@vmware.com>
Reply-To: akataria@vmware.com
To: Andi Kleen <andi@firstfloor.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>, LKML <linux-kernel@vger.kernel.org>,
       the arch/x86 maintainers <x86@kernel.org>,
       Daniel Hecht <dhecht@vmware.com>
In-Reply-To: <874p36fflp.fsf@basil.nowhere.org>
References: <1224552902.2640.88.camel@alok-dev1>
	 <874p36fflp.fsf@basil.nowhere.org>
Content-Type: text/plain
Organization: VMware INC.
Date: Tue, 21 Oct 2008 09:41:24 -0700
Message-Id: <1224607284.6161.22.camel@alok-dev1>
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On Tue, 2008-10-21 at 02:43 -0700, Andi Kleen wrote:
> Alok Kataria <akataria@vmware.com> writes:
> 
> > This patch set makes some changes to the TSC code, so that it is always
> > used as the default clocksource when running under VMware.
> 
> Does this imply that vmware always emulates TSC reads?
> Or how do you guarantee reliable TSC on a system where the underlying
> TSC isn't?

Yes the hypervisor takes care of providing constant rate TSC to the
guest.

> 
> It would be far nicer if VMware just emulated the "constant_tsc" bit
> in the AMD CPUID leaf, instead of adding all that gunk to Linux.
> Right now it's only checked for AMD CPUs, but that could be changed.

I am not sure if we might want to skip the tsc_sync code for all the
cpus which have this constant_tsc bit set, can we ?
Since i have seen that we can have cases where tsc is marked unstable as
its not found to be perfectly stable between cpus, we have to make sure
that we avoid this check when on VMware. Even with slight difference in
TSC between cpus, we know that TSC is the best available clocksource as
the hypervisor (VMware) makes sure that the drift is always marginal (if
ever there is).

Thanks,
Alok

> 
> Otherwise with more and more hypervisors we mind end up with more
> and more unscalable detection code.
> 
> -Andi
> 
> --
> ak@linux.intel.com

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