Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753532AbYKGOoV (ORCPT ); Fri, 7 Nov 2008 09:44:21 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1752121AbYKGOoN (ORCPT ); Fri, 7 Nov 2008 09:44:13 -0500 Received: from fg-out-1718.google.com ([72.14.220.152]:29553 "EHLO fg-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752116AbYKGOoM (ORCPT ); Fri, 7 Nov 2008 09:44:12 -0500 DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=message-id:date:from:reply-to:to:subject:cc:mime-version :content-type; b=V28anelUkO+GsGJpfv0FGXObZR7KNxUgFVVrbZ6zBWLRW5z8jA/gntU+PvFMSraapp wMuFniqW1doBMIzCIGuQw77EDqyHd7gVt0SKzf8L+YHMotw3fmkUxUeSS6WhLL2WMNen /2RpheyX3Cr7Hg2GfOlkv75ZBZZbfvmfTTLiY= Message-ID: <7c86c4470811070644h1f65ccdfi32c78fbf173abed9@mail.gmail.com> Date: Fri, 7 Nov 2008 15:44:09 +0100 From: "stephane eranian" Reply-To: eranian@gmail.com To: linux-kernel@vger.kernel.org Subject: [PATCH] x86 debugctl MSR access interface Cc: ananth@in.ibm.com, anil.s.keshavamurthy@intel.com, davem@davemloft.net, "Metzger, Markus T" MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_13936_28510990.1226069049612" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 16523 Lines: 239 ------=_Part_13936_28510990.1226069049612 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline Hello, On Intel X86 processors, the DEBUGCTL msr contains lots of bits to control various unrelated features, such as LBR, BTS, PMU. Nowadays, several subsystems need access to this MSR to set or clear the bits they care about. In 2.6.27, the new DS/BTS interface was introduced and DEBUGCTL can now be cleared and restored on context switches. The KPROBE interface also uses DEBUGCTL. In the context of perfmon, it can be interesting to also modify bits in DEBUGCTL, such as FREEZE_PMU_ON_PMI but also the bits controlling the LBR (bit 0 and 11). With perfmon, however, there are situations, e.g. LBR, where the DEBUGCTL bits are managed on a per-CPU level and not per-task level. Simply overwriting DEBUGCTL on context switch may conflict with per-cpu usage. It appears that modifications to DEBUGCTL must be done using a read-modify-write approach rather than pure write. To that extent, I would like to propose the attached patch which modifies the update_debugctlmsr() function to implement a read-modify-write access. The caller passes the value of debugctl and a mask of bits of interest. For instance, if you want to set bit 1 and clear bit 0, then you call update_debugctlmsr(0x2, 0x3). Please let me know what you think about this patch. Thanks. ------=_Part_13936_28510990.1226069049612 Content-Type: application/octet-stream; name=debugctl.diff Content-Transfer-Encoding: base64 X-Attachment-Id: f_fn8xpwij1 Content-Disposition: attachment; filename=debugctl.diff ZGlmZiAtLWdpdCBhL2FyY2gveDg2L2luY2x1ZGUvYXNtL2RzLmggYi9hcmNoL3g4Ni9pbmNsdWRl L2FzbS9kcy5oCmRpZmYgLS1naXQgYS9hcmNoL3g4Ni9pbmNsdWRlL2FzbS9wcm9jZXNzb3IuaCBi L2FyY2gveDg2L2luY2x1ZGUvYXNtL3Byb2Nlc3Nvci5oCmluZGV4IDVjYTAxZTMuLmM0ZWRkZDgg MTAwNjQ0Ci0tLSBhL2FyY2gveDg2L2luY2x1ZGUvYXNtL3Byb2Nlc3Nvci5oCisrKyBiL2FyY2gv eDg2L2luY2x1ZGUvYXNtL3Byb2Nlc3Nvci5oCkBAIC00MzAsNyArNDMwLDcgQEAgc3RydWN0IHRo cmVhZF9zdHJ1Y3QgewogCS8qIE1heCBhbGxvd2VkIHBvcnQgaW4gdGhlIGJpdG1hcCwgaW4gYnl0 ZXM6ICovCiAJdW5zaWduZWQJCWlvX2JpdG1hcF9tYXg7CiAvKiBNU1JfSUEzMl9ERUJVR0NUTE1T UiB2YWx1ZSB0byBzd2l0Y2ggaW4gaWYgVElGX0RFQlVHQ1RMTVNSIGlzIHNldC4gICovCi0JdW5z aWduZWQgbG9uZwlkZWJ1Z2N0bG1zcjsKKwl1bnNpZ25lZCBsb25nCWRlYnVnY3RsdmFsOwogI2lm ZGVmIENPTkZJR19YODZfRFMKIC8qIERlYnVnIFN0b3JlIGNvbnRleHQ7IHNlZSBpbmNsdWRlL2Fz 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