Message-ID: <492208BE.2000001@zytor.com>
Date: Mon, 17 Nov 2008 16:13:50 -0800
From: "H. Peter Anvin" <hpa@zytor.com>
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To: Venki Pallipadi <venkatesh.pallipadi@intel.com>
CC: Ingo Molnar <mingo@elte.hu>, Thomas Gleixner <tglx@linutronix.de>,
       linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] x86: Support always running TSC on Intel CPUs
References: <20081118001137.GA12350@linux-os.sc.intel.com>
In-Reply-To: <20081118001137.GA12350@linux-os.sc.intel.com>
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Venki Pallipadi wrote:
> Add support for CPUID_0x80000007_Bit8 on Intel CPUs as well. This bit means
> that the TSC is invariant with C/P/T states and always runs at constant
> frequency.
> 
> With Intel CPUs, we have 3 classes
> * CPUs where TSC runs at constant rate and does not stop n C-states
> * CPUs where TSC runs at constant rate, but will stop in deep C-states
> * CPUs where TSC rate will vary based on P/T-states and TSC will stop in deep
>   C-states.
> 
> To cover these 3, one feature bit (CONSTANT_TSC) is not enough. So, add a
> second bit (NOSTOP_TSC). CONSTANT_TSC indicates that the TSC runs at
> constant frequency irrespective of P/T-states, and NOSTOP_TSC indicates
> that TSC does not stop in deep C-states.
> 

What is the definition of a "deep" C-state?  C2?  C3?  C4?

	-hpa
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