Date: Thu, 4 Dec 2008 18:50:02 -0800
From: Arjan van de Ven <arjan@infradead.org>
To: David Miller <davem@davemloft.net>
Cc: paulus@samba.org, tglx@linutronix.de, linux-kernel@vger.kernel.org,
       linux-arch@vger.kernel.org, akpm@linux-foundation.org, mingo@elte.hu,
       eranian@googlemail.com, dada1@cosmosbay.com, robert.richter@amd.com,
       hpa@zytor.com, a.p.zijlstra@chello.nl, rostedt@goodmis.org
Subject: Re: [patch 2/3] performance counters: documentation
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On Thu, 04 Dec 2008 16:37:41 -0800 (PST)
David Miller <davem@davemloft.net> wrote:

> From: Paul Mackerras <paulus@samba.org>
> Date: Fri, 5 Dec 2008 11:33:31 +1100
> 
> > This is going to be a huge problem, at least on powerpc, because it
> > means that the kernel will have to know which events can be counted
> > on which counters and what values need to be put in the control
> > registers to select them.
> 
> Sparc64 is the same.
> 
> > The situation will be even worse with POWER5 and POWER6, where the
> > event selection logic is very complex, with multiple layers of
> > multiplexers.  I really really don't want the kernel to have to know
> > about all that.
> 
> Niagara2 has deep multiplexing and sub-event masking too.
> 
> I really appreciated how perfmon kept all of those details
> in userspace.

I would like to respectfully disagree with this some. The kernel needs
to abstract hardware to some degree for userspace. The problem in this
case is that userspace can't really do a better job, in fact it can
only do a worse job since it lacks the coordination capability of
knowing it has full control of all the hardware registers. 
I am sure the corner cases you're talking about are nasty, I just don't
think they are less nasty when dealt with in userspace. Sure the kernel
might be simpler, but the system as a whole sure is not.


-- 
Arjan van de Ven 	Intel Open Source Technology Centre
For development, discussion and tips for power savings, 
visit http://www.lesswatts.org
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