Date: Wed, 24 Dec 2008 18:32:38 +0000
From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: Robert Hancock <hancockr@shaw.ca>
Cc: linux-kernel@vger.kernel.org
Subject: Re: Memory vs. MMIO ordering, again
Message-ID: <20081224183238.3253d7b9@lxorguk.ukuu.org.uk>
In-Reply-To: <gittnv$2qj$1@ger.gmane.org>
References: <gittnv$2qj$1@ger.gmane.org>
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> MMIO accesses may, in effect, overtake accesses to cached memory that 
> were emitted earlier. A memory barrier isn't sufficient in such a case, 
> but rather the cache must be flushed between the cached memory write and 
> the MMIO access if the two are in any way dependent."
> 
> This seems like BS to me.. Flush the cache? How is a driver supposed to 
> know how to do that? Furthermore, why should it need to worry about this 
>   kind of detail? This seems wrong or at least a low-level detail that 
> normal code should not have to be concerned with.

There isn't really much choice in the matter. However if you are using
the normal pci_map_ and pci_alloc_coherent functions then those have your
cache management built into them and all you have to watch is compiler
funnies.

Alan
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