Date: Thu, 25 Dec 2008 00:11:44 +0000
From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: Robert Hancock <hancockr@shaw.ca>
Cc: linux-kernel@vger.kernel.org, dhowells@redhat.com
Subject: Re: Memory vs. MMIO ordering, again
Message-ID: <20081225001144.48423fea@lxorguk.ukuu.org.uk>
In-Reply-To: <4952A68E.2030906@shaw.ca>
References: <gittnv$2qj$1@ger.gmane.org>
	<20081224183238.3253d7b9@lxorguk.ukuu.org.uk>
	<4952A68E.2030906@shaw.ca>
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> What that documentation is suggesting is that MMIO writes to uncached 
> memory (what the normal mapping functions will give you) can pass 
> previous writes to cached memory. It doesn't indicate how this is to be 
> avoided, however.

They can. How you avoid it depends upon the bus but the problem is really
really rare as a corner case and almost the only device affected is
graphics because nobody uses cached memory on the PCI bus except graphics
cards and a couple of obscure other cases like I2O.

The graphics people implement various fencing operations and they are
generally tied down low level with AGP, GARTs and other places mere
mortals (ie most people except the DRI team) should not tread ;)

You need to distinguish between cachable memory remote on things like the
PCI bus (eg frame buffers) which are your problem and cachable memory in
the sense of main memory, which is handled by the pci_map functions or
kept coherent if allocated via the PCI coherent memory allocator - in
which case all you have to watch is the compiler and write buffers on the
CPU.

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