From: Herbert Xu <herbert@gondor.apana.org.au>
To: ying.huang@intel.com (Huang Ying)
Subject: Re: [RFC PATCH crypto] AES: Add support to Intel	AES-NI	instructions
Cc: herbert@gondor.apana.org.au, suresh.b.siddha@intel.com,
        linux-crypto@ml.breakpoint.cc, akpm@linux-foundation.org,
        linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org,
        mingo@elte.hu, tglx@linutronix.de
Organization: Core
In-Reply-To: <1229476462.5936.314.camel@yhuang-dev.sh.intel.com>
User-Agent: tin/1.7.4-20040225 ("Benbecula") (UNIX) (Linux/2.6.17-rc4 (i686))
Message-Id: <E1LClB3-0006WP-9J@gondolin.me.apana.org.au>
Date: Wed, 17 Dec 2008 12:26:17 +1100
Sender: linux-kernel-owner@vger.kernel.org

Huang Ying <ying.huang@intel.com> wrote:
>
> f. if TS is clear, then use x86_64 implementation. Otherwise if
> user-space has touched the FPU, we save the state, if not then simply
> clear TS.

Well I'd rather avoid using the x86_64 implementation ever because
unless the chip guys have really screwed up we should be looking at
a difference of at least a factor of 10.

BTW I wasn't very clear in the original email.  You'd only do the
asynchronous operation for CBC/ECB.  For the simple AES case I
suppose we'll just have to stick to the x86_64 fallback.  This'll
really suck for disk encryption but I guess you could always add
an LRW/XTS mode to your code.

Cheers,
-- 
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Email: Herbert Xu ~{PmV>HI~} <herbert@gondor.apana.org.au>
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