Date: Tue, 06 Jan 2009 11:06:42 +0900 (JST)
Message-Id: <20090106.110642.130607183.nemoto@toshiba-tops.co.jp>
To: dan.j.williams@intel.com
Cc: anemo@mba.ocn.ne.jp, haavard.skinnemoen@atmel.com,
       linux-kernel@vger.kernel.org, hskinnemoen@atmel.com,
       maciej.sosnowski@intel.com, ralf@linux-mips.org
Subject: Re: [PATCH] dmatest: flush and invalidate destination buffer
 before DMA
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
In-Reply-To: <4962B414.8010601@intel.com>
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	<20090106.101425.109407744.nemoto@toshiba-tops.co.jp>
	<4962B414.8010601@intel.com>
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On Mon, 05 Jan 2009 18:29:56 -0700, Dan Williams <dan.j.williams@intel.com> wrote:
> > Yes, MIPS and ARM do different thing on partial cache line.  But I
> > suppose this belongs to "implementation dependent" area of DMA API so
> > users of the API should not depend on it.  (Well, maybe I'm biased to
> > MIPS ;-))
> > In general, drivers must not put normal data and DMA buffer on same
> > cacheline anyway to avoid unexpected writeback and data loss.  So this
> > ambiguity is not a problem.  IMHO writeback of the partial line for
> > DMA_FROM_DEVICE just _hides_ abusing of the DMA API and potential data
> > loss.
> 
> Hmm... one implementation does the right thing in all cases.

Yes, with additional checking in generic path :-)

> The other silently allows data corruption unless each callsite that
> accidentally or purposely passes cacheline-unaligned buffers adds
> extra maintenance code.  Which implementation are you biased towards
> now? :-).

Hmm... this is generic DMA mapping API (or linux-arch) issue.  Let's
wait comments from arch maintainers.  Ralf ?

---
Atsushi Nemoto
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