From: Vadim Lobanov <vlobanov@speakeasy.net>
To: Thomas Dahlmann <dahlmann.thomas@arcor.de>
Subject: Re: amd5536udc interrupts bug
Date: Thu, 8 Jan 2009 10:27:18 -0800
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On Thursday 08 January 2009 08:40:28 Thomas Dahlmann wrote:
> Ah, right. Thanks for your analysis! Never ran into this condition as on
> the Geode systems I had the IRQ is shared between UDC and 
UOC/OTG
> (both on the CS5536 chip) and UOC never fires interrupts while UDC
> driver is loaded as both drivers (UOC/OTG driver is not in the kernel 
yet)
> register each other which makes sure that interrupts are enabled
> after  udc_pci_probe().

Ok, I understand.

> I could provide a fix within the next weeks. Currently I move to another
> company and
> have no hardware to test it.

No worries. :) I can also test your patches on my board here, if it helps 
any.

> Maybe you want to try this. It should work to place the register init
> from udc_probe()
>
> /* udc csr registers base */
> dev->csr = dev->virt_addr + UDC_CSR_ADDR;
> /* dev registers base */
> dev->regs = dev->virt_addr + UDC_DEVCFG_ADDR;
> /* ep registers base */
> dev->ep_regs = dev->virt_addr + UDC_EPREGS_ADDR;
> /* fifo's base */
> dev->rxfifo = (u32 __iomem *)(dev->virt_addr + UDC_RXFIFO_ADDR);
> dev->txfifo = (u32 __iomem *)(dev->virt_addr + UDC_TXFIFO_ADDR);
>
> just before request_irq(...) to allow the interrupt handler to read the
> interrupt status
> registers.

I'll slip this into the next kernel build and see what happens. Thanks!

-- Vadim Lobanov

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