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Date: Mon, 18 Feb 2002 11:22:06 -0800
From: "H. Peter Anvin" <hpa@zytor.com>
Organization: Zytor Communications
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To: george anzinger <george@mvista.com>
CC: linux-kernel@vger.kernel.org, "Grover, Andrew" <andrew.grover@intel.com>
Subject: Re: Missed jiffies
In-Reply-To: <3C6E77DE.70FE49DF@rwii.com> <3C6E833F.1A888B3C@mvista.com> <a4pbvi$iq2$1@cesium.transmeta.com> <3C715036.EBC74D72@mvista.com>
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george anzinger wrote:

> "H. Peter Anvin" wrote:
> 
>>Followup to:  <3C6E833F.1A888B3C@mvista.com>
>>By author:    george anzinger <george@mvista.com>
>>In newsgroup: linux.dev.kernel
>>
>>>One of the nasty problems, especially with machines such as yours (i.e.
>>>lap tops), is the fact that TSC is NOT clocked at a fixed rate.  It is
>>>affected by throttling (reduced in 12.5% increments) and by power
>>>management.
>>>
>>If the TSC is affected by HLT, throttling, or C2 power management, the
>>TSC is broken (as it is on Cyrix chips, for example.)  The TSC usually
>>*is* affected by C3 power management, but the OS should be aware of
>>C3.
>>
> Gosh I would LIKE to think this is true.  Could you give a reference?  I
> believe Andrew Grover thinks that what I have stated is true.  If I am
> wrong, it will make the high-res-timers MUCH more acceptable as the TSC
> overhead is MUCH lower that the ACPI pm timer.
> 
> Do I have this right Andrew?
> 


What I have defined above is what Linux considers a "working" TSC.  I
belive this to be functional on Intel, AMD and Transmeta CPUs.

However, there are some systems -- especially using older chips with less
PLL delays -- which change CLKIN on the fly.

	-hpa



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