Date: Thu, 29 Jan 2009 22:47:40 -0700 (MST)
From: Paul Walmsley <paul@pwsan.com>
To: Russell King - ARM Linux <linux@arm.linux.org.uk>
cc: linux-arm-kernel@lists.arm.linux.org.uk, linux-kernel@vger.kernel.org,
       linux-omap@vger.kernel.org, Tony Lindgren <tony@atomide.com>
Subject: Re: [PATCH C 06/13] OMAP3 clock: DPLLs should enter bypass if new
 rate is sys_ck
In-Reply-To: <20090129123936.GA16644@n2100.arm.linux.org.uk>
Message-ID: <alpine.DEB.2.00.0901292244211.26985@utopia.booyaka.com>
References: <20090128190724.12092.22239.stgit@localhost.localdomain> <20090128190823.12092.2638.stgit@localhost.localdomain> <20090129123936.GA16644@n2100.arm.linux.org.uk>
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Hello Russell,

this E-mail responds to your comments on patches C 04 through C 08.  
My understanding is that you'd like me to:

1. Compress patches C 04 through C 09;

2. Modify omap3_noncore_dpll_enable() to move the "if (!ret)
   clk->rate = rate" outside and below the conditional;

3. Remove some of the blank lines before and after braces in C 06;

4. Modify the DPLL bypass clock handling to change the DPLL's clk->parent,
   rather than return the bypass clock rate.

The above all make sense to me, and #4, if it works in practice, should be 
a significant improvement over the existing code.

If this is what you're looking for, I'll send a compressed, modified 
patch.  Would you like it to be based on the codebase post C 03, or 
against another commit?

regards,

- Paul

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