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Message-ID: <0a5301c1b981$a921f820$1a01a8c0@allyourbase>
From: "Dan Maas" <dmaas@dcine.com>
To: "Jesse Barnes" <jbarnes@sgi.com>, "David Mosberger" <davidm@hpl.hp.com>
Cc: <linux-kernel@vger.kernel.org>,
        "Benjamin Herrenschmidt" <benh@kernel.crashing.org>,
        "Ben Collins" <bcollins@debian.org>
In-Reply-To: <092401c1b8e7$1d190660$1a01a8c0@allyourbase> <15474.34580.625864.963930@napali.hpl.hp.com> <20020219103506.A1511175@sgi.com>
Subject: Re: readl/writel and memory barriers
Date: Tue, 19 Feb 2002 15:11:45 -0500
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Jesse Barnes wrote:
> To avoid the overhead of having I/O flushed on every
> memory barrier and readX/writeX operation, we've introduced
> mmiob() on ia64, which explicity orders I/O space accesses.
> Some ports have chosen to take the performance hit in every
> readX/writeX, memory barrier, and spinlock however
> (e.g. PPC64, MIPS).

I have a hunch that many drivers will break if you change the semantics of
readX/writeX from in-order to out-of-order - lots of drivers are only
developed & tested on x86, which completely hides the issue...

If you consider the performance cost of in-order readX/writeX to be
significant, then I would suggest adding another group of readX/writeX APIs
that explicitly allow out-of-order PCI access. (__raw_readX/__raw_writeX
seem to offer this already on some platforms...)

Regards,
Dan

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