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From: David Mosberger <davidm@hpl.hp.com>
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Date: Wed, 20 Feb 2002 11:08:25 -0800
To: Rik van Riel <riel@conectiva.com.br>
Cc: Mike Fedyk <mfedyk@matchmail.com>, Ville Herva <vherva@twilight.cs.hut.fi>,
        george anzinger <george@mvista.com>, <linux-kernel@vger.kernel.org>
Subject: Re: jiffies rollover, uptime etc.
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>>>>> On Wed, 20 Feb 2002 14:24:42 -0300 (BRT), Rik van Riel <riel@conectiva.com.br> said:

  Rik> On Wed, 20 Feb 2002, Mike Fedyk wrote:

  >> What's the difference between these two architectures?  Intel
  >> 64bit processor and AMD's upcoming 64bit processor?

  Rik> One is a 64 bit extension to a modern superscalar architecture
  Rik> which has descended from 8 bit machines over the ages.

Interesting opinion.

  Rik> The other is a 3-issue VLIW follow-up to the 2-issue VLIW i860.

There are some factual errors in this statement:

The ia64 _architecture_ places no limit on how many instructions can
be issued at a time.  You could have an instruction group that's
thousands of instructions long which could all be executed in a single
cycle.  Of course, realistic CPUs will bound the number of
instructions that can be issued in parallel.  The Itanium and McKinley
_implementations_ of ia64 happen to issue up to 6 instructions at a
time, but other issue-widths are possible.

To the best of my knowledge, i860 had virtually no influence on ia64.
Cydrome's Cydra5 and Multiflow's TRACE did, as did PA-RISC.

Thanks,

	--david
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