Date: Mon, 20 Apr 2009 00:35:19 +0200
From: Ingo Molnar <mingo@elte.hu>
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: Roland Dreier <rdreier@cisco.com>, Thomas Gleixner <tglx@linutronix.de>,
       "Robert P. J. Day" <rpjday@crashcourse.ca>,
       Hitoshi Mitake <h.mitake@gmail.com>,
       Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: arch/x86/Kconfig selects invalid HAVE_READQ, HAVE_WRITEQ vars
Message-ID: <20090419223519.GA27706@elte.hu>
References: <alpine.LFD.2.00.0904191543530.11789@localhost.localdomain> <adaab6c1h7c.fsf@cisco.com> <20090419214602.GA21527@elte.hu> <49EB9F59.4080904@zytor.com>
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* H. Peter Anvin <hpa@zytor.com> wrote:

> Ingo Molnar wrote:
> > 
> > Look at the drivers that define their own wrappers:
> > 
> > #ifndef readq
> > static inline unsigned long long readq(void __iomem *addr)
> > {
> >         return readl(addr) | (((unsigned long long)readl(addr + 4)) << 32LL);
> > }
> > #endif
> > 
> > ... it's the obvious 32-bit semantics for reading a 64-bit value 
> > from an mmio address. We made that available on 32-bit too.
> > 
> > It's being used ... and has been in use for some time. Where's 
> > the problem? readl is serializing on all default-ioremap mmio 
> > targets on x86 so there's no ambiguity in ordering.
> 
> I think his point is that they're not atomic. [...]

Ok - i didnt really consider atomicity, because that's not really 
feasible for a number of reasons anyway:

> [...] For what it's worth, atomic readq()/writeq() *are* possible 
> with any x86-32 CPU which supports MMX, but it is very costly to 
> do in the kernel since it involves touching the FPU state.
> 
> For the vast number of users, a non-atomic primitive which is 
> available for both 32- and 64-bit x86 is a win.  For a small 
> number of users, it'll be confusing, and for a very small minority 
> it's going to be desirable to have the atomic primitive.
> 
> The reason the non-atomic is generally fine is because most device 
> drivers are inherently single-threaded on a per-hardware device 
> basis.

Also, atomicity might not be possible to guarantee on the bus level: 
say the device sits on a 32-bit PCI bus. (No matter what instruction 
the CPU gets, a readq/writeq there has to be done as two 32-bit bus 
accesses.)

(Also, even a genuine 64-bit device might be bridged over 32-bit 
pathways so a driver cannot really assume atomicity on that level.)

	Ingo
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