Message-ID: <3C8691C9.30FA3C29@mandrakesoft.com>
Date: Wed, 06 Mar 2002 17:01:45 -0500
From: Jeff Garzik <jgarzik@mandrakesoft.com>
Organization: MandrakeSoft
MIME-Version: 1.0
To: Ion Badulescu <ionut@cs.columbia.edu>
CC: linux-kernel@vger.kernel.org
Subject: Re: [PATCH] starfire net driver update for 2.4.19pre2
In-Reply-To: <Pine.LNX.4.44.0203061652050.31906-100000@age.cs.columbia.edu>
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Sender: linux-kernel-owner@vger.kernel.org

Ion Badulescu wrote:
> 
> On Wed, 6 Mar 2002, Jeff Garzik wrote:
> 
> > There is a bugfix, which I will make locally before submitting:
> > PCI_COMMAND_INVALIDATE should be enabled -after- messing with
> > PCI_CACHE_LINE_SIZE.
> 
> I didn't find anything in the starfire chipset's documentation about this,
> so is there a deeper reason for this ordering? As far as I know, most if
> not all x86 PCI chipsets silently map MWI to MW, so it should only matter
> for non-x86 plaforms, right?

More PCI than a Starfire requirement.

And there are plenty of ia32 platforms that benefit from MWI, too. 
Often its server mobos that support MWI, but some cheaper ones do too.


> And, in general, are there any other tricks one can do to speed up the PCI
> transactions on non-x86 platforms? I'm still getting occasional overruns
> on sparc64 (card receiving packets faster than it can push them over PCI),
> which is somewhat disturbing..

Dynamically tune your RX and TX DMA burst settings when you notice these
conditions...  It is indeed possible to saturate PCI bus bandwidth.

	Jeff


-- 
Jeff Garzik      | Usenet Rule #2 (John Gilmore): "The Net interprets
Building 1024    | censorship as damage and routes around it."
MandrakeSoft     |
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