From: "Pan, Jacob jun" <jacob.jun.pan@intel.com>
To: Pavel Machek <pavel@ucw.cz>
CC: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
       "H. Peter Anvin" <hpa@linux.intel.com>
Date: Thu, 2 Jul 2009 16:09:09 -0700
Subject: RE: [PATCH 2/9] x86: introduce a set of platform feature flags
Thread-Topic: [PATCH 2/9] x86: introduce a set of platform feature flags
Thread-Index: Acn6Knv4XHqeI486RqmNZq950/cs2gBPsvAw
Message-ID: <43F901BD926A4E43B106BF17856F07556428B555@orsmsx508.amr.corp.intel.com>
References: <43F901BD926A4E43B106BF17856F07556412B7E1@orsmsx508.amr.corp.intel.com>
 <20090630063230.GD1351@ucw.cz>
In-Reply-To: <20090630063230.GD1351@ucw.cz>
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>> +#define platform_has(bit) \
>> +	test_bit(bit, (unsigned long *)platform_feature)
>
>test_bit and friends imply synchronization you probably  don't want or
>need...
>
[[JPAN]] could you explain a little more? The disassembly shows the test_bit
ends up as a testb instruction and a jump. Why there is synchronization
 involved?
Perhaps on some architectures?
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