Date: Sat, 11 Jul 2009 00:51:23 +0100
From: Jamie Lokier <jamie@shareable.org>
To: "Kirill A. Shutemov" <kirill@shutemov.name>
Cc: ARM Linux Mailing List <linux-arm-kernel@lists.arm.linux.org.uk>,
       linux-kernel@vger.kernel.org,
       Siarhei Siamashka <siarhei.siamashka@nokia.com>
Subject: Re: [PATCH] ARM: copy_page.S: take into account the size of the cache line
Message-ID: <20090710235123.GE30322@shareable.org>
References: <1247156605-16245-1-git-send-email-kirill@shutemov.name>
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Kirill A. Shutemov wrote:
> From: Kirill A. Shutemov <kirill@shutemov.name>
> 
> Optimized version of copy_page() was written with assumption that cache
> line size is 32 bytes. On Cortex-A8 cache line size is 64 bytes.
> 
> This patch tries to generalize copy_page() to work with any cache line
> size if cache line size is multiple of 16 and page size is multiple of
> two cache line size.
> 
> Unfortunately, kernel doesn't provide a macros with correct cache size.
> L1_CACHE_SHIFT is 5 on any ARM. So we have to define macros for this
> propose by ourself.

Why don't you fix L1_CACHE_SHIFT for Cortex-A8?

-- Jamie
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