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	 <20090907204913.2aef5c49@infradead.org>
Date: Tue, 8 Sep 2009 13:09:44 +0800
Message-ID: <3877989d0909072209g454d92feuc0d3cdbd95a13a9c@mail.gmail.com>
Subject: Re: [RFC PATCH] C2 could be mapped to C3 so need a flush cache
From: Luming Yu <luming.yu@gmail.com>
To: Arjan van de Ven <arjan@infradead.org>
Cc: LKML <linux-kernel@vger.kernel.org>, Len Brown <lenb@kernel.org>,
       "Pallipadi, Venkatesh" <venkatesh.pallipadi@intel.com>,
       "Siddha, Suresh B" <suresh.b.siddha@intel.com>
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On Tue, Sep 8, 2009 at 11:49 AM, Arjan van de Ven<arjan@infradead.org> wrote:
> On Tue, 8 Sep 2009 10:26:06 +0800
> Luming Yu <luming.yu@gmail.com> wrote:
>
>> Hi there,
>>
>> I came across acpi_idle_enter_simple, noticed it looks like a bug if
>> we don't flush cache for C2.
>> Because some platforms just map C2 to C3.
>
> I think you are confusing ACPI C3 with HW C3.
>
> Only for ACPI C3 class do you need to flush the cache for this case.
> For HW C3, if you would need to flush the cache, the BIOS would assign
> it ACPI C3 class.
>

There is no confusion,I just extend the existing kernel logic as below
to cover cache flush..

"
"/*
 * Some BIOS implementations switch to C3 in the published C2 state.
 * This seems to be a common problem on AMD boxen, but other vendors
 * are affected too. We pick the most conservative approach: we assume
 * that the local APIC stops in both C2 and C3.
 */
static void lapic_timer_check_state

"
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