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Date: Sat, 16 Mar 2002 11:57:26 -0700
From: yodaiken@fsmlabs.com
To: Linus Torvalds <torvalds@transmeta.com>
Cc: yodaiken@fsmlabs.com, Paul Mackerras <paulus@samba.org>,
        linux-kernel@vger.kernel.org
Subject: Re: [Lse-tech] Re: 10.31 second kernel compile
Message-ID: <20020316115726.B19495@hq.fsmlabs.com>
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In-Reply-To: <Pine.LNX.4.33.0203161037160.31913-100000@penguin.transmeta.com>; from torvalds@transmeta.com on Sat, Mar 16, 2002 at 10:45:46AM -0800
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On Sat, Mar 16, 2002 at 10:45:46AM -0800, Linus Torvalds wrote:
> 
> On Sat, 16 Mar 2002 yodaiken@fsmlabs.com wrote:
> 
> > On Sat, Mar 16, 2002 at 10:06:06AM -0800, Linus Torvalds wrote:
> > > We'll end up (probably five years from now) re-doing the thing to allow 
> > > four levels (so a tired old x86 would fold _two_ levels instead of just 
> > > one, but I bet they'll still be the majority), simply because with three 
> > > levels you reasonably reach only about 41 bits of VM space.
> > 
> > Why so few bits per level? Don't you want bigger pages or page clusters?
> 
> Simply because I want to be able to share the software page tables with 
> the hardware page tables.

Isn't this only an issue when the hardware wants to search the tables?
So for a semi-sane architecture, the hardware idea of pte is only important
in the tlb.

is there a 64 bit machine with hardware search of pagetables? Even ibm
only has a hardware search of hash tables - which we agree are simply
a means of making your hardware TLB larger and slower.





-- 
---------------------------------------------------------
Victor Yodaiken 
Finite State Machine Labs: The RTLinux Company.
 www.fsmlabs.com  www.rtlinux.com

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