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From: David Mosberger <davidm@napali.hpl.hp.com>
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Date: Sat, 16 Mar 2002 11:43:29 -0800
To: Linus Torvalds <torvalds@transmeta.com>
Cc: <yodaiken@fsmlabs.com>, Paul Mackerras <paulus@samba.org>,
        <linux-kernel@vger.kernel.org>
Subject: Re: [Lse-tech] Re: 10.31 second kernel compile
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>>>>> On Sat, 16 Mar 2002 11:16:16 -0800 (PST), Linus Torvalds <torvalds@transmeta.com> said:

  >> is there a 64 bit machine with hardware search of pagetables?
  >> Even ibm only has a hardware search of hash tables - which we
  >> agree are simply a means of making your hardware TLB larger and
  >> slower.

  Linus> ia64 does the same mistake, I think.

ia64 has an optional hardware walker which can operate in "hashed"
mode or in "virtually mapped linear page table mode".  If you think
you can do a TLB lookup faster in software, you can turn the walker
off.  Our experience so far is that the hw walker does help
performance significantly.  This is partly because it allows CPU
designers to play some nice tricks, which you can't do once the miss
is exposed to software.  Also, since it's defined as an optional
feature, the hardware doesn't have to deal with the difficult corner
cases.  If it gets "overwhelmed" for one reason or another, it can
simply throw up it's hands and raise a TLB miss fault.

Anyhow, at the moment ia64 linux operates the hardware walker in the
virtually mapped linear page table mode, which allows us to use the
normal Linux page tables for the hardware walker.  However, I think
it's quite possible (perhaps even quite likely) that at some time
during the 2.5 cycle we'll switch the hardware walker into hashed
mode.  At that point, the hardware walker would simply operate as
large in-core TLB.  If Linux had a more flexible page table
abstraction, we could treat the in-core TLB as the primary page table,
but quite frankly, it's not clear at all to me whether and how much of
a win this would be.

	--david
--
Interested in learning more about IA-64 Linux?  Try http://www.lia64.org/book/
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