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Date: Sat, 16 Mar 2002 12:57:11 -0700
From: yodaiken@fsmlabs.com
To: Andi Kleen <ak@suse.de>
Cc: yodaiken@fsmlabs.com, Paul Mackerras <paulus@samba.org>,
        linux-kernel@vger.kernel.org, torvalds@transmeta.com
Subject: Re: [Lse-tech] Re: 10.31 second kernel compile
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In-Reply-To: <p73g0301f79.fsf@oldwotan.suse.de>; from ak@suse.de on Sat, Mar 16, 2002 at 08:32:26PM +0100
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On Sat, Mar 16, 2002 at 08:32:26PM +0100, Andi Kleen wrote:
> x86-64 aka AMD Hammer does hardware (or more likely microcode) search of 
> page tables.
> It has a 4 level page table with 4K pages. Generic Linux MM code only sees
> the first slot in 4th level page limit user space to 512GB with 3 levels. 

What about 2M pages?

> Direct mappings and kernel mappings are handled specially by architecture 
> specific code outside that first slot.
> 
> The CPU itself has I/D TLBs split into L1 and L2.

There was something in some AMD doc about preventing tlbflush on process
switch - through a context like thing perhaps? Any idea?


> 
> -Andi

-- 
---------------------------------------------------------
Victor Yodaiken 
Finite State Machine Labs: The RTLinux Company.
 www.fsmlabs.com  www.rtlinux.com

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