Date: Sat, 19 Sep 2009 16:08:21 +0200
From: Borislav Petkov <borislav.petkov@amd.com>
To: Keith Mannthey <kmannth@us.ibm.com>
CC: lkml <linux-kernel@vger.kernel.org>, dougthompson@xmission.com
Subject: Re: [Patch] AMD64_EDAC: Fix amd64_map_to_dcs_mask
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On Fri, Sep 18, 2009 at 10:28:53AM -0700, Keith Mannthey wrote:
> > Almost. You have 8 DCSMs on RevE, 4 on RevF and F10h and 2 on F11h and
> > this way you get wrong DCSM offsets for F11h. A dirty fix would be:
> 
> I think this will still be ok for F11. 
> 
> 
> ilog2(2) = 1 
> 
> 1 + 1 == 2 
> 
> 8 >> 2 == 2 
> 
> csrow >> 2 
> 
> This would be ok rev F11 assuming 8 total. 
> 
> Am I missing something else?

Yes, F11h has only 4 DCSB and 2 DCSM registers. So the first
two DCSB registers F2x[1,0]40 and F2x[1,0]44 use F2x[1,0]60 as
a mask register and F2x[1,0]48 and F2x[1,0]4C use F2x[1,0]64.
You can look at F11h as a F10h but with only the half of the
DSC[BM] registers present. You can find the F11h BKDG at
http://support.amd.com/us/Processor_TechDocs/41256.pdf and especially
Table 24 on page 115.

So, in that case csrow >> 1 is still valid but csrow going beyond 3 is
out of range that's why it needs to be fixed differently.

> Are there more than 8 csrows any any version (I don't currently have
> F11 specs). Maybe should just move to a map rather than a math trick
> to get to the right index?

I'll think up something on Monday.

> > By the way, your patches made me look harder at that code region and
> > I've found some more problems with it which I've fixed. Would you
> > like to test the whole bunch of fixes on your setup?
>
> Yes please send any changes you have. I have a decent test setup for
> live errors.

Cool, I'll get back to you when I have them ready, thanks.

-- 
Regards/Gruss,
Boris.

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