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Date: Mon, 12 Oct 2009 22:31:46 -0400
From: Theodore Tso <tytso@mit.edu>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: "Carlos R. Mafra" <crmafra2@gmail.com>, Eric Anholt <eric@anholt.net>,
       linux-kernel@vger.kernel.org, Keith Packard <keithp@keithp.com>
Subject: Re: 2.6.32 regression (bisected): Video tearing/glitching with
	T400 laptops
Message-ID: <20091013023146.GA8414@mit.edu>
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	Jesse Barnes <jbarnes@virtuousgeek.org>,
	"Carlos R. Mafra" <crmafra2@gmail.com>,
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	Keith Packard <keithp@keithp.com>
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On Mon, Oct 12, 2009 at 12:05:10PM -0700, Jesse Barnes wrote:
> On Mon, 12 Oct 2009 20:46:51 +0200
> "Carlos R. Mafra" <crmafra2@gmail.com> wrote:
> 
> > On Mon 12.Oct'09 at  9:54:38 -0700, Jesse Barnes wrote:
> > > > 
> > > > Nope, unfortunately, it's not helping on my T400 laptop.  I'm
> > > > still getting huge amounts of glitching and tearing with this
> > > > patch applied against -rc3.
> > > > 
> > > > What I'm using for now to fix up my system is this patch.
> > > > 
> > > 
> > > How about this one?  I have one more idea to try out if this doesn't
> > > work (hacking on it now).
> > 
> > I was also experiencing something very similar to Theodore's bug 
> > report and, at least for me, the patch below fixed the issue (the
> > previous one also had no effect).
> 
> Cool, good to hear.  Hopefully Ted and Keith will confirm too.

Hmm, the amount of tearing seems to be a bit less frequent, but it's
definitely still happening with this patch applied.  Sorry....

	   	 	   	     - Ted


> -- 
> Jesse Barnes, Intel Open Source Technology Center
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7a5fb79..1451945 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1047,7 +1047,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
>  	dev_priv->cfb_fence = obj_priv->fence_reg;
>  	dev_priv->cfb_plane = intel_crtc->plane;
>  
> -	dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
> +	dpfc_ctl = plane | DPFC_CTL_LIMIT_1X;
>  	if (obj_priv->tiling_mode != I915_TILING_NONE) {
>  		dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
>  		I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
--
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