Date: Mon, 26 Oct 2009 13:39:34 -0700
From: Jesse Barnes <jesse.barnes@intel.com>
To: Dave Jones <davej@redhat.com>
Cc: Linux Kernel <linux-kernel@vger.kernel.org>
Subject: Re: [X86] PCI: Use generic cacheline sizing instead of per-vendor
 tests.
Message-ID: <20091026133934.57320657@jbarnes-g45>
In-Reply-To: <20091014203139.GA2336@redhat.com>
References: <20091014203139.GA2336@redhat.com>
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On Wed, 14 Oct 2009 16:31:39 -0400
Dave Jones <davej@redhat.com> wrote:

> Instead of the PCI code needing to have code to determine the 
> cacheline size of each processor, use the data the cpu identification
> code should have already determined during early boot.
> 
> (The vendor checks are also incomplete, and don't take into account
>  modern CPUs)
> 
> I've been carrying a variant of this code in Fedora for a while,
> that prints debug information.  There are a number of cases where we
> are currently setting the PCI cacheline size to 32 bytes, when the CPU
> cacheline size is 64 bytes.  With this patch, we set them both the
> same.
> 
> Signed-off-by: Dave Jones <davej@redhat.com>

Applied this; had to fix up a few conflicts due to Tejun's recent CLS
improvements though...

-- 
Jesse Barnes, Intel Open Source Technology Center
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