Date: Wed, 18 Nov 2009 20:52:40 -0800
From: Arjan van de Ven <arjan@infradead.org>
To: Ingo Molnar <mingo@elte.hu>
Cc: Nick Piggin <npiggin@suse.de>, Jan Beulich <JBeulich@novell.com>,
       tglx@linutronix.de, linux-kernel@vger.kernel.org, hpa@zytor.com,
       Ravikiran Thirumalai <kiran@scalex86.org>,
       Shai Fultheim <shai@scalemp.com>
Subject: Re: [PATCH] x86: eliminate redundant/contradicting cache line size
 config options
Message-ID: <20091118205240.11d3d660@infradead.org>
In-Reply-To: <20091119035640.GA18236@elte.hu>
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	<20091116105657.GE5818@wotan.suse.de>
	<20091119035640.GA18236@elte.hu>
Organization: Intel
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On Thu, 19 Nov 2009 04:56:40 +0100
Ingo Molnar <mingo@elte.hu> wrote:

> 
> * Nick Piggin <npiggin@suse.de> wrote:
> 
> > The only other use for L1 cache size macro is to pack objects to 
> > cachelines better (so they always use the fewest number of lines).
> > But this case is more rare nowadays people don't really count
> > cachelines anymore, but I think even then it makes sense for it to
> > be the largest line size in the system because we don't know how
> > big L1s are, and if you want opimal L1 packing, you likely also
> > want optimal Ln packing.
> 
> We could do that - but then this default of X86_INTERNODE_CACHE_SHIFT:
> 
> +       default "7" if NUMA
> 
> will bite us and turns the 64 bytes L1_CACHE_BYTES into an effective
> 128 bytes value.
> 
> So ... are you arguing for an increase of the default x86 linesize to 
> 128 bytes?

128 is basically always wrong.
(unless you have a P4... but for default really we should not care
about those anymore)


-- 
Arjan van de Ven 	Intel Open Source Technology Centre
For development, discussion and tips for power savings, 
visit http://www.lesswatts.org
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