Date: Thu, 19 Nov 2009 07:59:58 -0800
From: Arjan van de Ven <arjan@infradead.org>
To: Nick Piggin <npiggin@suse.de>
Cc: Ingo Molnar <mingo@elte.hu>, Jan Beulich <JBeulich@novell.com>,
       tglx@linutronix.de, linux-kernel@vger.kernel.org, hpa@zytor.com,
       Ravikiran Thirumalai <kiran@scalex86.org>,
       Shai Fultheim <shai@scalemp.com>
Subject: Re: [PATCH] x86: eliminate redundant/contradicting cache line size
 config options
Message-ID: <20091119075958.2cba15f8@infradead.org>
In-Reply-To: <20091119081307.GA20534@wotan.suse.de>
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Organization: Intel
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On Thu, 19 Nov 2009 09:13:07 +0100
Nick Piggin <npiggin@suse.de> wrote:
> 
> My other point was just this, but I don't care too much. But it is
> worded pretty negatively. The key here is that increasing the value
> too large tends to only cost a very small amount of size (and no
> increase in cacheline foot print, only RAM). 

128 has a pretty significant impact on TPC-C benchmarks.....
it was the top issue until mainline fixed it to default to 64

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