Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751924AbZKZScT (ORCPT ); Thu, 26 Nov 2009 13:32:19 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751721AbZKZScS (ORCPT ); Thu, 26 Nov 2009 13:32:18 -0500 Received: from gateway-1237.mvista.com ([206.112.117.35]:49958 "HELO imap.sh.mvista.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with SMTP id S1751512AbZKZScR (ORCPT ); Thu, 26 Nov 2009 13:32:17 -0500 Message-ID: <4B0EC9EA.9000608@ru.mvista.com> Date: Thu, 26 Nov 2009 21:33:14 +0300 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Bartlomiej Zolnierkiewicz Cc: Alan Cox , linux-ide@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] pata_it8213: MWDMA0 is unsupported References: <200911261728.36433.bzolnier@gmail.com> <200911261903.01199.bzolnier@gmail.com> <4B0EC52B.2070805@ru.mvista.com> <200911261927.00597.bzolnier@gmail.com> In-Reply-To: <200911261927.00597.bzolnier@gmail.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1848 Lines: 56 Bartlomiej Zolnierkiewicz wrote: >>>>>>>MWDMA0 timings cannot be met with the PIIX based controller >>>>>>>programming interface. >>>>>>>This change should be safe as this is how we have been doing >>>>>>>things in IDE it8213 host driver for years. >>>>>>>Signed-off-by: Bartlomiej Zolnierkiewicz >>>>>>>--- >>>>>>>Verified with the documentation (similar case as with pata_efar). >>>>>>Uhhh, no... >>>>>>Too many damn drivers. >>>>>>Too much damn duplication. >>>>>>Too much damn subtle differences here and there. >>>>>>The hardware is probably fine for MWMDA0 when it comes to pata_{efar,it8213}, >>>>>>it just not documented properly in the data sheet. >>>>> How so with pata_efar? The active/recovery bitfields are still 2-bit >>>>>wide, no? >>>>Yes but when TIMEx bit is disabled we are using XFER_PIO_SLOW timings. >> 600 ns cycle vs spec'ed 480 ns? Is it really worth it? > 960 ns actually That table you're looking at (probably in the SLC90E66 datasheet?) must be screwed up. 960 ns is used for command cycles, according to Intel's docs, data cycles run at 600 ns... >>>>All data sheets including original Intel ones are a complete crap when it >>>>comes to explicitly documenting this behavior. >>>OTOH all drivers set TIMEx for MWDMA0 currently.. ? >> >> ... which would give a grossly overclocked timing. > Except ata_piix which blacklists MWDMA0 for _all_ PATA controllers.. :) :-) > I'm leaving my patches as they were for now, unless somebody wants to > untangle this mess this is a safest and quickest way forward.. MBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/