Message-ID: <4B102CE5.1050901@ru.mvista.com>
Date: Fri, 27 Nov 2009 22:47:49 +0300
From: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Organization: MontaVista Software Inc.
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To: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>, linux-ide@vger.kernel.org,
       linux-kernel@vger.kernel.org
Subject: Re: [PATCH] pata_hpt3x2n: fix overclocked MWDMA0 timing
References: <200911271956.55939.bzolnier@gmail.com> <4B102B83.1080102@ru.mvista.com>
In-Reply-To: <4B102B83.1080102@ru.mvista.com>
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Hello, I wrote:

>> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
>> ---
>> Sergei, XFER_UDMA_5 timing also looks suspicious,
>> please take a look when you have a minute, thanks.

>    Yeah, but it's the same as XFER_UDMA_4, so actually underclocked... 
> However, it matches what the HPT371N datasheet and the vendor drivers 
> have. The 'hpt366' driver uses more speedy mode, with 22.5 ns cycle. ;-)

    I have just verified: this driver has always used this timing 
historically, at least for HPT372+ chips.

MBR, Sergei

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