Date: Fri, 11 Dec 2009 13:48:35 +0100
From: Ingo Molnar <mingo@elte.hu>
To: Jamie Iles <jamie.iles@picochip.com>
Cc: David Miller <davem@davemloft.net>, linux-kernel@vger.kernel.org,
       linux@arm.linux.org.uk, peterz@infradead.org
Subject: Re: [PATCH 1/2] perf tools: allow building for ARM
Message-ID: <20091211124835.GB14509@elte.hu>
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 <20091211.023808.233094506.davem@davemloft.net>
 <20091211104126.GA22079@elte.hu>
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* Jamie Iles <jamie.iles@picochip.com> wrote:

> On Fri, Dec 11, 2009 at 11:41:26AM +0100, Ingo Molnar wrote:
> > > I think he did it this way so it can compile in the meantime, and that 
> > > doing it right requires runtime cpu detection to select which barrier 
> > > instruction is even available on the current ARM cpu.
> > 
> > Yeah. We can merge a quick patch for it if runtime detection is 
> > difficult - but if then such a patch should err on the side of using the 
> > barrier instruction unconditionally - even if this causes perf to 
> > segfault on certain (older? UP configured?) ARM cores.
>
> Ok, unless anyone has any objections, I'll post a revised patch that 
> uses the MCR instruction so that we get the correct behaviour on v6/v7 
> SMP and UP systems and an illegal instruction on v5 or earlier. I've 
> had a quick look at runtime detection and the ID registers are only 
> accessible from privileged modes so for long term, it might be better 
> to define the rmb() at build time from the kernel config.

Sounds good to me.

	Ingo
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