From: Arnd Bergmann <arnd@arndb.de>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [BISECTED] drm: random hang since 620f378 "drm: prune modes when ..."
Date: Tue, 15 Dec 2009 10:51:43 +0100
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Cc: Dave Airlie <airlied@redhat.com>, Daniel Vetter <daniel@ffwll.ch>,
       Adam Jackson <ajax@redhat.com>, linux-kernel@vger.kernel.org,
       dri-devel@lists.sourceforge.net, keithp@keithp.com, eric@anholt.net,
       Daniel Vetter <daniel.vetter@ffwll.ch>
References: <200912071830.14697.arnd@arndb.de> <200912142038.09254.arnd@arndb.de> <20091214125024.77601d7e@jbarnes-piketon>
In-Reply-To: <20091214125024.77601d7e@jbarnes-piketon>
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On Monday 14 December 2009, Jesse Barnes wrote:
> This patch removes the suspect portion of the dynamic clock control
> code.  Hopefully it'll be as stable as powersave=0 in your config
> (assuming powersave=0 works :).

Ok, great! The machine is still running  fine with powersave=0 so 
far. I'll try your patch after some more uptime.

	Arnd

> Jesse Barnes, Intel Open Source Technology Center
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_d
> index 279dc96..b8730de 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3825,8 +3825,6 @@ void intel_decrease_renderclock(struct drm_device *dev)
>                 /* Down to minimum... */
>                 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
>                 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
> -
> -               pci_write_config_word(dev->pdev, GCFGC, gcfgc);
>         } else if (IS_I965G(dev)) {
>                 u16 gcfgc;

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