Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1765310AbZLQSIl (ORCPT ); Thu, 17 Dec 2009 13:08:41 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1765300AbZLQSIh (ORCPT ); Thu, 17 Dec 2009 13:08:37 -0500 Received: from caramon.arm.linux.org.uk ([78.32.30.218]:60679 "EHLO caramon.arm.linux.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1765298AbZLQSIg (ORCPT ); Thu, 17 Dec 2009 13:08:36 -0500 Date: Thu, 17 Dec 2009 18:08:03 +0000 From: Russell King To: Linus Torvalds Cc: Christoph Hellwig , tytso@mit.edu, Kyle McMartin , linux-parisc@vger.kernel.org, Linux Kernel Mailing List , James.Bottomley@suse.de, linux-arch@vger.kernel.org, Jens Axboe Subject: Re: [git patches] xfs and block fixes for virtually indexed arches Message-ID: <20091217180802.GA1546@flint.arm.linux.org.uk> Mail-Followup-To: Linus Torvalds , Christoph Hellwig , tytso@mit.edu, Kyle McMartin , linux-parisc@vger.kernel.org, Linux Kernel Mailing List , James.Bottomley@suse.de, linux-arch@vger.kernel.org, Jens Axboe References: <20091216043618.GB9104@hera.kernel.org> <20091217132256.GO28962@bombadil.infradead.org> <20091217163036.GE2123@thunk.org> <20091217170743.GA10431@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1617 Lines: 41 On Thu, Dec 17, 2009 at 09:42:15AM -0800, Linus Torvalds wrote: > You both flush the virtual caches before > the IO and invalidate after - when the real pattern should be that you > flush it before a write, and invalidate it after a read. That's not entirely true. If you have write back caches which are not DMA coherent, you need to as a minimum: - on write, clean the cache to ensure that the page is up to date with data held in cache. - on read, you must ensure that there are no potential write-backs before the read commenses and invalidate at some point. The point at which you invalidate depends on whether the CPU speculatively prefetches: - If it doesn't, you can invalidate the cache before the read, thereby destroying any potential writebacks, and the cache will remain unallocated for that address range until explicitly accessed. - If you do have a CPU which does prefetch speculatively, then you do need to clean the cache before DMA starts, and then you must invalidate after the DMA completes. Invalidating after DMA completes for the non-speculative prefetch just wastes performance, especially if you have to do so line by line over a region. With ARM architecture version 7, we now have ARM CPUs which fall into both categories. -- Russell King Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/ maintainer of: -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/