Subject: Re: [PATCH] perf_events: improve Intel event scheduling
From: Peter Zijlstra <peterz@infradead.org>
To: Paul Mackerras <paulus@samba.org>
Cc: Stephane Eranian <eranian@google.com>, eranian@gmail.com,
       linux-kernel@vger.kernel.org, mingo@elte.hu,
       perfmon2-devel@lists.sf.net, "David S. Miller" <davem@davemloft.net>
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Date: Thu, 07 Jan 2010 10:00:26 +0100
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On Thu, 2010-01-07 at 15:13 +1100, Paul Mackerras wrote:
> 
> > All the enable and disable calls can be called from NMI interrupt context
> > and thus must be very careful with locks.
> 
> I didn't think the pmu->enable() and pmu->disable() functions could be
> called from NMI context.

I don't think they're called from NMI context either, most certainly not
from the generic code.

The x86 calls the raw disable from nmi to throttle the counter, but all
that (should) do is disable that counter, which is limited to a single
msr write. After that it schedules a full disable by sending a self-ipi.


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