From: Robert Richter <robert.richter@amd.com>
To: Peter Zijlstra <a.p.zijlstra@chello.nl>,
       Stephane Eranian <eranian@googlemail.com>
CC: Paul Mackerras <paulus@samba.org>, Ingo Molnar <mingo@elte.hu>,
       LKML <linux-kernel@vger.kernel.org>
Subject: [PATCH 01/12] perf/core: x86 and AMD pmu updates
Date: Fri, 22 Jan 2010 15:21:55 +0100
Message-ID: <1264170127-17402-1-git-send-email-robert.richter@amd.com>
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I know there is some ongoing work by Stephane in this code too, but I
want to submit the patches anyway for review. If necessary I will
rebase the patch set on top of Stephanes patches. Anyway, this patch
set applies to tip/perf/core and can be pulled from here too:

 git://git.kernel.org/pub/scm/linux/kernel/git/rric/oprofile.git perf

The patches contain changes, updates and code reworks I made during
reviewing the code and implementing IBS for perf_events. Patches for
IBS I will submit in a later series. These patches will include an
implementation that extends the ABI to support model specific hardware
pmu features.

In this patch set I made some model specific pmu code generic and vice
versa. The event constraint handler works now for AMD pmu too. Fixed
counter code that is only need on Intel cpus is now model
specific. Also the MSR masks were unified, where the hardware
implementation is the same for all cpus.

-Robert


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