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Date: Wed, 27 Jan 2010 08:48:54 -0800
From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: davidjon@xenontk.org
Cc: yakui.zhao@intel.com,
       "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: Fix For Korg Bug #14897 (GM45 Display Flicker)
Message-ID: <20100127084854.6da89284@jbarnes-piketon>
In-Reply-To: <4B60080E.2000508@xenontk.org>
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On Wed, 27 Jan 2010 15:01:58 +0530
David John <davidjon@xenontk.org> wrote:

> Hi Jesse, Yakui,
> 
> Sorry for the delay, but I was busy with other work last week. I got
> some time to look into this on Monday and the problem seems to be this:
> 
> With the external display connected on VGA, intel_update_watermarks
> calls update_wm a couple of times in sequence with the following params:
> 
> 1) planea_clock = 148500 planeb_clock = 0, sr_hdisplay=1920 (VGA)
> 2) planea_clock = 148500 planeb_clock = 72330, sr_hdisplay=1366 (LVDS)
> 
> In update_wm (in my case g4x_update_wm), for 1) sr_entries is calculated
> correctly and self refresh is enabled. For 2) sr_entries remains zero
> and the SR watermark is set as such. However, SR remains
> active. On mode switch to console, this causes a FIFO underrun and the
> display flicker.

Ugg that's not supposed to happen.  With both planes enabled
self-refresh shouldn't be active afaik.  I guess we'll actually have to
flip the bit and turn it off in that case.

> The solution that I see is to simply disable SR if more than one pipe is
> enabled. I've written a patch that does this. Also another point is that
> the G45 docs state that a particular sequence has to be followed if SR
> is to be used when only one pipe is active for Cantiga (Pg 30, G45 Vol
> 3). I didn't see any code doing this, but I did not see any untoward
> behaviour either, with only my patch applied.

Great, I'll look for it and ack it.

> I've updated the patch to fix i965 and i9xx as I assume the same problem
> will occur on those chipsets as well, but this has _not_been tested as I
> don't have the relevant platforms.

Yeah, it's probably the safe thing to do.

> 
> Patch follows this mail. Please let me know if any changes are required.
> 
> The VGA output powering-on on mode change mentioned in my bug report is
> a separate DRM bug for which I will send a patch later.

Thanks a lot.

-- 
Jesse Barnes, Intel Open Source Technology Center
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