Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id ; Wed, 17 Apr 2002 08:47:24 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id ; Wed, 17 Apr 2002 08:47:23 -0400 Received: from fgwmail5.fujitsu.co.jp ([192.51.44.35]:14286 "EHLO fgwmail5.fujitsu.co.jp") by vger.kernel.org with ESMTP id ; Wed, 17 Apr 2002 08:47:21 -0400 Date: Wed, 17 Apr 2002 21:47:54 +0900 Message-ID: From: Shuji YAMAMURA To: jbourne@MtRoyal.AB.CA Cc: linux-kernel@vger.kernel.org, mingo@elte.hu Subject: Re: SMP P4 APIC/interrupt balancing In-Reply-To: In your message of "Tue, 16 Apr 2002 16:29:32 -0600 (MDT)" User-Agent: Wanderlust/1.1.1 (Purple Rain) SEMI/1.13.7 (=?ISO-2022-JP?B?GyRCMEBERRsoQg==?=) CLIME/1.13.6 (=?ISO-2022-JP?B?GyRCQ2YlTj4xGyhC?=) Emacs/20.7 (i386-vine-linux-gnu) MULE/4.1 (=?ISO-2022-JP?B?GyRCMCobKEI=?=) Organization: Fujitsu Laboratories MIME-Version: 1.0 (generated by SEMI 1.13.7 - =?ISO-2022-JP?B?IhskQjBAGyhC?= =?ISO-2022-JP?B?GyRCREUbKEIi?=) Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org At Tue, 16 Apr 2002 16:29:32 -0600 (MDT), James Bourne wrote: > Hi All, > Ok, we have a Dell PE4600 with dual P4X processors. It will not balance > interrupts between the two cpus, CPU0 always receives the bulk > of the interrupts, although both processors are being utilized > by processes on the system. This system is not yet in production, so I > have some time to try things on it. > > Current kernel is 2.4.18 with the LSE APIC Routing patch > (http://sourceforge.net/projects/lse). 2.4.18 stock (well ok, -rc4) has > much the same results. We observed the similar problem on our i860 based P4 SMP machine. We examined several tests and got the following fact: - Only the upper 4 bits of the task priority is effective on Pentium 4. The LSE APIC Routing patch assigns values from 0x10 to 0x18 to TPR for setting task priority, that means the upper 4 bits are always '0001'. Based on the previous obserbation, these values are useless in terms of proper interrupt distribution. To get an expected operation, upper 4 bits must be changed. You may refer the following thread that talks this problem. "P4 SMP load balancing" http://marc.theaimsgroup.com/?t=100287923700006&r=1&w=2 Appendix. Our experiments were examined on two different systems. The following table shows the relations between the TPR value of each CPU and the interrupt destination. Pentium4 Machine: CPU: Pentium4 Xeon 2.0GHz x 2 Motherboard: Supermicro P4DCE Chipset: Intel860 Pentium3 Machine: CPU: Pentium3 500MHz x 2 Motherboard: ASUS CUR-DLS Chipset: Serverworks ServerSet3 LE Boot Processor: CPU#0 TPR Value Interrupt CPU CPU#0 CPU#1 Pen3 Pen4 ========================================= 01 02 0or1 0 02 01 0or1 0 0f 00 0or1 0 ----------------------------------------- 10 01 1 1 10 11 0 0 11 10 1 0 1f 10 1 0 11 11 0or1 0 ----------------------------------------- 20 20 0or1 0 20 10 1 1 20 21 0 0 21 20 1 0 ----------------------------------------- ---- Shuji YAMAMURA Grid Computing & Bioinformatics Laboratory, FUJITSU Laboratories, LTD. E-mail: yamamura@flab.fujitsu.co.jp - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/