Date: 3 Feb 2010 18:56:44 -0500
Message-ID: <20100203235644.3084.qmail@science.horizon.com>
From: "George Spelvin" <linux@horizon.com>
To: catalin.marinas@arm.com
Subject: Re: USB mass storage and ARM cache coherency
Cc: linux@horizon.com, linux-kernel@vger.kernel.org
Sender: linux-kernel-owner@vger.kernel.org
Content-Length: 796
Lines: 16

> Apart from that, flush_dcache_page() doesn't have any data flow
> information. Optimisations could be done on ARM if we know that the
> kernel only intends to read from a page (no flushing necessary with a
> non-aliasing D-cache).

Already done in flush_dcache_page().  If possible (uniprocessor), it just
flags the page as PG_dcache_dirty, and defers the actual flush operation
until it's mapped somewhere else (either a virtual alias or executable).

See Documentation/cachetlb.txt.  (Really, all PIO drivers should
be calling flush_dcache_page.)
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